1. Field of the Invention
The present invention relates to a semiconductor memory, particularly to a semiconductor memory provided with a data-line equalizing circuit for setting each data line constituting a data-line pair to the same predetermined voltage before reading data from a memory cell.
2. Description of the Background Art
In the case of a dynamic random access memory (DRAM), the equalizing operation for setting each data line constituting a data-line pair for transferring stored data to the same predetermined voltage is performed before reading data from a memory cell.
FIG. 12 is a circuit diagram showing a configuration of the circumference of a data-line equalizing circuit (hereafter also merely referred to as equalizing circuit) of a conventional DRAM.
Referring to FIG. 12, a memory cell MC for keeping stored data has an access transistor AT and a storage capacitor SC for keeping a voltage level of a data storage node Nm.
FIG. 12 shows the so-called shared-sense-amplifier configuration, and a sense-amplifier circuit SA is shared by data-line pairs DRP and DLP separately arranged. The stored data of one memory cell MC typically shown in FIG. 12 is transferred by the data-line pair DRP. The data-line pair DRP has a data line DR electrically connected with a data storage node Nm in the memory cell MC through the access transistor AT and a data line /DR for transferring the data complementary with the data line DR. Similarly, the data-line pair DLP has a data lines DL and /DL for transferring the data complementary with each other.
In the case of a DRAM conforming to the shared-sense-amplifier configuration, switching circuits 6 and 7 for connecting/disconnecting two data-line pairs DRP and DLP with/from the sense-amplifier circuit SA are set between the pairs DRP and DLP on one hand and the circuit SA on the other. The switching circuits 6 and 7 are respectively constituted of an N-channel MOS transistor. Specifically, the switching circuit 6 has N-channel MOS transistors M1L and M2R receiving a control signal DLIR by their gates. Similarly, the switching circuit 7 has N-channel MOS transistors M1L and M2L receiving a control signal DLIL by their gates.
The data-line pairs DRP and DLP further share an equalizing circuit 8. The equalizing circuit 8 has an N-channel MOS transistor M3 for connecting both data lines constituting a data-line pair and N-channel MOS transistors M4 and M5 for connecting each data line constituting a data-line pair with a predetermined precharge-voltage (Vdd/2) node. A data-line-equalizing signal DLEQ is input to gates of the transistors M3, M4, and M5.
A precharge voltage is generally set to Vdd/2 which is an intermediate voltage between a power-supply voltage Vdd corresponding to H level of stored data and a ground voltage Vss corresponding to L level of the stored data in order to reduce the power consumption and noises accompanying charge/discharge of a data line.
An external power-supply voltage ExVdd is supplied to a DRAM from the outside of a chip. A power-supply voltage Vdd stepped down from ExVdd by a not-illustrated VDC (Voltage Down Converter) or a step-up voltage Vpp (Vpp greater than Vdd) stepped up from ExVdd by a Vpp generation circuit 2 are generated in the DRAM.
The transistors used for switching circuits 6 and 7, equalizing circuit 8, and access transistor AT are frequently respectively constituted of only an N-channel MOS transistor in order to reduce an area. In this case, to transfer the power-supply voltage Vdd corresponding to H level of stored data, it is necessary to set the gate voltage of an N-channel MOS transistor to Vdd+Vth (Vth: threshold voltage of N-channel MOS transistor) or higher.
Therefore, the step-up voltage Vpp (Vpp greater than Vdd) is used for each H-level potential of control signals DLIR and DLIL input to the gate of an N-channel MOS transistor constituting the switching circuits 6 and 7. Specifically, the control signals DLIR and DLIL are generated by signal buffers 3 and 4 driven by the step-up voltage Vpp.
Also for a word line WL for turning on the access transistor AT, an activated voltage level is set to the step-up voltage Vpp by a word-line driver WD driven by the step-up voltage Vpp.
It is only necessary for the N-channel MOS transistors M3 to M5 constituting the equalizing circuit 8 to transfer the precharge voltage Vdd/2 of a data line. Therefore, it is unnecessary to use a step-up voltage for a voltage when a data-line equalizing signal DLEQ input to gates of these transistors is activated, that is, an H-level voltage as long as the H-level voltage meets the following expression (1).
ExVdd greater than Vth+Vdd/2xe2x80x83xe2x80x83(1)
Therefore, a signal buffer 5 for generating the data-line equalizing signal DLEQ is driven by the external power-supply voltage ExVdd, and the H-level voltage of the data-line equalizing signal DLEQ has been generally set to ExVdd.
FIG. 13 is a timing chart for explaining the data read operation of the DRAM shown in FIG. 12.
Referring to FIG. 13, the data-line equalizing signal DLEQ and control signals DLIR and DLIL are respectively activated to an H-level voltage before data is read. As already described, H-level voltages of the control signals DLIR and DLIL are respectively equal to the step-up voltage Vpp, and the H-level voltage of the data-line equalizing signal DLEQ is equal to ExVdd.
Thereby, the transistors M1R, M1L, M2R, M2L, and M3 to M5 constituting the switching circuits 6 and 7 and the equalizing circuit 8 are all turned on. As a result, the data lines DR and /DR are set to the same precharge voltage Vdd/2. Data lines DL/DL are also set to the same precharge voltage Vdd/2 (not shown). Thus, the equalizing operation of a data line is executed before the data read operation.
When the data read operation is started, either of the switching circuits 6 and 7 is turned on and only one data-line pair is connected with the sense amplifier SA. In FIG. 13, to disconnect the data-line pair DLP from the sense amplifier SA, the transistors M1L and M2L constituting the switching circuit 7 are turned off in response to inactivation (to L-level voltage Vss) of the control signal DLIL.
Similarly, the data-line equalizing signal DLEQ is inactivated to the L-level voltage (Vss), and the transistors M3 to M5 constituting the equalizing circuit 8 are turned off.
Under the above state, the word line WL is activated to the H-level voltage (step-up voltage Vpp). In response to the above operation, the access transistor AT is turned on, and the data storage node Nm is connected with the data line DR. FIG. 13 shows a case in which the memory cell MC keeps H-level data. Therefore, the voltage level of the data line DR is slightly stepped up by electric charges stored in the storage capacitor SC in response to turn-on of the access transistor AT. However, the voltage level of the complementary data line /DL is kept at the precharge voltage Vdd/2.
Thereafter, the sense-amplifier circuit SA is further activated and voltage levels of power-supply nodes SP and SN are set to the power-supply voltage Vdd and ground voltage Vss. Thereby, a minute voltage difference generated between the data lines DR and /DR is amplified, and voltage levels of the data lines DR and /DR are set to Vdd and Vss. Thus, data is normally read from the DRAM by assuming the normal equalizing operation of the data lines.
As described above, the data-line-equalizing signal DLEQ for controlling the equalizing circuit 8 is generally driven by the external power-supply voltage ExVdd.
Recently, however, a DRAM is frequently mounted on portable information terminal units that have been rapidly spread. It is requested for these portable information terminal units to operate for a long time by a battery having a limited power-supply capacity. Therefore, it is requested that the power consumption of an electronic device mounted on a portable information terminal unit is minimized. Because the power consumption of an electronic device is almost proportional to the second power of an operating power-supply voltage, it is effective to lower a power-supply voltage for reduction of power consumption. Therefore, it is strongly requested for a DRAM to lower the external power-supply voltage ExVdd supplied from an external unit.
However, there is a problem in simply lowering the power-supply voltage Vdd in a DRAM in accordance with lowering of the external power-supply voltage ExVdd. The electric-charge quantity stored in the memory cell MC correspondingly to stored data is decided by the product of the capacitance of the storage capacitor SC and the power-supply voltage Vdd. Therefore, when lowering the power-supply voltage Vdd, the electric-charge quantity stored in the memory cell MC decreases and is subject to the influence of noises or the like. Moreover, because the power-supply voltage Vdd is also used for the driving power-supply voltage of the sense-amplifier circuit SA, when lowering the power-supply voltage Vdd, operations of the sense-amplifier circuit SA are decelerated and it is difficult to accelerate data read.
Moreover, it is difficult to simply lower the threshold voltage Vth of an N-channel MOS transistor correspondingly to lowering of the external power-supply voltage ExVdd. This is because by lowering the threshold voltage Vth, a leak current (subthreshold current) increases, when the access transistor AT is turned off and electric charges stored in the memory cell MC are easily lost. As a result, it is necessary to shorten a refresh cycle and thereby, power consumption increases.
Because of these factors, when keeping the H-level voltage of the data-line equalizing signal DLEQ at the external power-supply voltage ExVdd, gate voltages of the transistors M3 to MS constituting the equalizing circuit 8 cannot meet the above expression (1) as the external power-supply voltage ExVdd lowers. Thereby, it is impossible to sufficiently transfer the precharge voltage Vdd/2 by the transistors M3 to M5. As a result, it is impossible to normally execute the precharge operation of a data line before the data read operation and thereby, data may not be normally read.
It is an object of the present invention to provide a semiconductor-memory configuration capable of normally executing the equalizing operation of a data line by an N-channel MOS transistor even if an external power-supply voltage is lowered.
In short, the present invention is a semiconductor device operating with an external power-supply voltage, which is provided with first and second data lines, a plurality of memory cells, and a data-line equalizing circuit. The first and second data lines transmit a data signal having two data levels. One of the data levels of the data signal corresponds to a first voltage. The memory cells hold the stored data. Each memory cell includes a storage node for storaging the data level of the data signal and a data transfer gate for electrically connecting the storage node with either of the first and second data lines in response to activation of a word line set to a second voltage higher than the first voltage. The data-line equalizing circuit sets the first and second data lines to the same predetermined voltage in response to a control signal. The control signal is set to a third voltage higher than the external power-supply voltage but lower than the second voltage when activated.
Another aspect of the present invention is a semiconductor device operating with an external power-supply voltage, which is provided with first and second data lines, first and second voltage generation circuits, a plurality of memory cells, and a data-line equalizing circuit. The first and second data lines transmit a data signal having two data levels. One of data levels of the data signal corresponds to a first voltage. The first internal-voltage generation circuit receives the external power-supply voltage and generates a first internal voltage higher than the first voltage. The second internal-voltage generation circuit receives the external power-supply voltage and outputs a second internal voltage higher than the external power-supply voltage but lower than the first internal voltage. The memory cells hold stored data. Each memory cell includes a storage node for storaging the data level and a first data transfer gate for electrically connecting the storage node with either of the first and second data lines in response to activation of a word line set to the first internal voltage. The data-line equalizing circuit sets the first and second data lines to the same predetermined voltage in response to an equalizing control signal. The equalizing control signal is set to the second internal voltage when activated.
Still another aspect of the present invention is a semiconductor device which is provided with a memory cell, a data line pair, a word line, a sense-amplifier circuit, and a data-line equalizing circuit. The memory cell includes a capacitor for storing charges and an access transistor. The data line pair includes two data lines. One of the two data lines is connected to the memory cell. The word line is connected to the gate of the access transistor and is set to a first voltage under activation. The sense-amplifaier circuit amplifies a small voltage difference between the two data lines to a voltage difference between the ground voltage and a second voltage. The small voltage difference is generated representing the stored charges in the capacitor in response to the activation of the word line. The data-line equalizing circuit sets each of the two data lines to one same predetermined voltage in response to a control signal. The control signal is set to a third voltage higher than an external power-supply voltage and lower than the first voltage under activation.
Therefore, the main advantage of the present invention lies in the fact that it is possible to normally execute the precharge and equalizing operations of the first and second data lines by setting the level of a control signal to a proper voltage when activated without using an excessively-high voltage even if an external power-supply voltage is lowered.
Moreover, because the second internal voltage used as a step-up voltage is lower than the first internal voltage for activating a word line, it is possible to downsize the second internal-voltage generation circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.